The present disclosure relates generally to Peripheral Component Interconnect (PCI) devices, and more particularly to shared interrupt lines utilized by multiple PCI devices.
PCI is a local computer bus standard for attaching hardware devices in a computer. The PCI bus supports various functions found on a processor bus in a standardized format that is independent of a particular processor's native bus. PCI devices that are connected to the PCI bus are assigned addresses in the processor's address space.
When a PCI device needs attention from the processor, it sends an interrupt signal by asserting an interrupt line. The interrupt line stays asserted until the processor has handled the interrupt request of the PCI device. Specifically, the driver for the device will handle the interrupt request and then cause the interrupt line to be de-asserted after the interrupt request is appropriately handled.
In many cases, multiple PCI devices share the same interrupt line. Thus, when the interrupt line is asserted, the system must first determine what device is seeking attention. After handling that interrupt, the system can then check to see if the line is still asserted. It may be the case that another device on the same interrupt line is also seeking attention. When all interrupts have been handled, the interrupt line should then be de-asserted. It is desirable to manage the interrupts in an efficient manner.